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NXP Semiconductors /LPC18xx /EEPROM /RWSTATE

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Interpret as RWSTATE

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RPHASE20RPHASE10RESERVED

Description

EEPROM read wait state register

Fields

RPHASE2

Wait states 2 (minus 1 encoded). The number of system clock periods to meet the read operations TRPHASE2 duration.
RPHASE1

Wait states 1 (minus 1 encoded). The number of system clock periods to meet a duration equal to TRPHASE1.
RESERVED

Reserved. Read value is undefined, only zero should be written.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data